Electronic packages of the variety described above are known in the art. Examples are defined in detail in U.S. Pat. Nos. 5,435,732 (Angulas et al), 5,397,921 (Karnezos), 5,386,341 (Olson et al), 5,278,724 (Angulas et al), 4,873,123 (Canestaro et al) and 5,383,787 (Switky et al).
As defined therein, such packages typically include a semiconductor device (chip) electrically coupled to one side of a circuitized substrate such as a flexible circuit member, which typically comprises a dielectric, e.g., polyimide, having at least one layer of circuitry, e.g., copper thereon. Such a chip may be coupled, electrically, to the flexible circuit member's circuitry using solder. See, e.g., U.S. Pat. No. 5,435,732 at FIG. 10. A well-known technique for accomplishing such a solder coupling includes what is known in the industry as a controlled collapse chip connection (C4) procedure. Another known process is a thermal compression bonding (TCB) procedure. Because both processes are known, further description is not believed necessary. The flexible circuitry (often called a tape) may then be coupled electrically to respective circuitry, e.g. copper pads or lines, formed on the surfaces of a circuitized substrate, such as another flex circuit, a more rigid printed circuit board, a ceramic substrate, or the like. Circuit boards, usually comprised of several layers of dielectric material, e.g., fiberglass-reinforced epoxy resin, interspersed with various conductor levels, e.g., power, signal and/or ground planes, and often including plated through-holes and/or internal conductive vias, are known in the art and further definition is not believed necessary.
The above packages also typically utilize a heat sink member which is thermally coupled to the package's chip, the heat sink being located slightly above the chip and provided with a good thermal path to the chip to enhance heat removal from the completed package (most particularly the chip) during package operation. Such heat sinks usually comprise a metallic element located on the package in such a position as to facilitate thermal removal by interaction with a cooling airflow or, simply, relatively non-moving ambient air. The heat sink may be attached to the chip with an appropriate thermal adhesive, several of which are known in the art. To further promote heat removal, the heat sink typically includes appropriate fins, pins, or the like at various locations. The heat sink may also be of a multilayer (or multilevel) design, where each level of the heat sink is optimized for a particular function. The first level of the heat sink may be designed to optimize the thermal contact with the chip and the removal and spreading of heat from the chip, along with the function of protecting the chip and attached circuitry from chemical or other contact from various manufacturing processes. The heat sink's second level may be optimized for thermal interaction with cooling fluid flow (gas or liquid) to provide additional thermal efficiency if demanded by a particular application. This second level of the heat sink may be a separate element, attached to the first level structure by thermal adhesive. It is possible that the first heat sink level may comprise a low-profile, platelike member with the second level including a plurality of fins so that in combination, very high rates of heat removal may be realized. However, if very high thermal performance is not needed, the second level of heat sink may be omitted.
In U.S. Pat. No. 5,397,921, an example is shown of a chip electrically connected to a tape by at least two methods. A one-level heat sink design is used, with the heat sink material chosen to be a specifically designed metallic compound so as to match the coefficient of thermal expansion (CTE) of the heat sink to that of the chip. However, such a choice will not adequately match the CTE of the tape to the chip. Since the chip is bonded to the tape, there exists a mismatch in expansion coefficients, and thus thermally-induced stresses will occur on the circuitry of the tape. Such stresses, typically the result of temperature changes during package operation, can adversely affect the package, including possibly rendering it inoperative.
To utilize various thermal epoxies for heat sink attachment, the temperature of the entire package must be elevated during production in order to cure the epoxy into a useful material state. Because of the mismatch of thermal expansion coefficients between the tape and chip, high tensile stresses are thus created between the chip and the bulk of the tape. These stresses have occasionally resulted in wrinkling of the tape, which in turn results in substantial, unpredictable, and uncontrollable non-planarity of portions of the tape. Such non-planarity can interfere with subsequent electrical connection procedures involving the package's circuitry. Such interference can be great enough to render the package unusable or can contribute to unreliable subsequent electrical connections. This mechanism of failure is further aggravated by the use of larger size chips which are considered necessary in many of today's electronic package assemblies in order to assure enhanced operational capabilities demanded of such structures.
It is also known that some procedures of electrically connecting the chip to the circuitry of the tape (a/k/a chip bonding) require the use of substantially elevated chip temperatures. A primary example is the aforementioned TCB procedure, which requires relatively high temperatures and pressures to satisfactorily effect chip and tape connections. As the connection is formed, the temperature of the chip is significantly greater than that of the bulk of the tape. Subsequent cooling of the bonded chip and tape results in high tensile stresses between both elements. As mentioned, such stresses have been found of sufficient magnitude to induce wrinkles in the tape.
In accordance with the teachings of the present invention, it has been found that it is possible to avoid the condition of high tensile stresses, which cause the condition of tape wrinkling, by the use of strain relief means between the chip and the tape. Significantly, use of this invention permits the highly advantageous utilization of larger and more complex chips in such electronic packages, thereby advancing the art of electronics and electronic packaging in general. Further, such use of strain relief in turn permits the use of a wide variety of high-temperature cured thermal adhesives with such larger chips, while preventing tape wrinkling.
For a chip package to accommodate numerous sizes, designs and types of chips, it is not always possible to precisely know what the effective CTE of a chip will be. Therefore, it is not possible to choose the heat sink material CTE to match that of the chip, as there is known to be a range of chip material CTE values depending on the exact chip material composition (e.g., silicon or gallium arsenide), processing and coating of the chip material, and the extent of circuitry on the chip. Even if the CTE of the heat sink material was perfectly matched to that of the chip, temperature gradients or differences between the heat sink and the chip may cause an unacceptable expansion mismatch. Thus, for a variety of practical reasons, there will in general exist a mismatch of expansion between the chip and the heat sink, giving rise to thermally induced stresses in any thermal epoxy used to bond the two members. As understood, these stresses can be substantial, causing fracture, debonding, and loss of thermal contact between heat sink and chip. Such conditions may also lead to chip overheating and disconnection from the tape. In order to avoid these failures, the present invention also details a means of reducing these stresses and improving the adhesion between the adhesive and heat sink, if such adhesive is utilized. Further, a simple means of providing additional support and bracing to promote contact between the chip and heat sink is described. This additional support can be necessary if a relatively large, massive heat sink is required, and the strength of the thermal adhesive (e.g., epoxy) alone is not sufficient. As understood from the following, implementation of this invention will enable the successful use of relatively large, heavy heat sinks, made of a heat sink material which is not necessarily chosen to be a particular match to any of a wide variety of large, complex, and varied chips.
Because the chip is bonded to the tape, and there exists a relatively significant mismatch in expansion coefficients, small thermally-induced stresses can occur during use of the tape's circuitry. These stresses are not necessarily of the high tensile nature described above (which can cause wrinkling), but instead are relatively small and may occur at the location of the circuitry on the tape that is directly coupled to the chip. The action of heating an electronic package and subsequently cooling thereof is known as thermal cycling. It is known that even very small stresses can induce fatigue fracture in the circuitry after a relatively large number of such cycles, such fatigue fracture possibly resulting in a loss of electrical conductivity of a circuit line (and thus failure of the entire package). To reduce these stresses, it has been found that providing a fillet of a particular configuration can also be effective as stress relief means. These stresses can also be redirected away from circuit lines near the chip (which are relatively fine and narrow) to more robust electrical lines farther away from the chip, using the teachings of the invention.
It is believed that an electronic package assembly possessing the above and other advantageous features which is thus capable of overcoming the several aforementioned problems, and a method of making such a package assembly, would constitute significant advancements in the art.